Hardware Development Toolchain

The hardware tool chain described here are the software tools required to convert from a VHDL or Verilog design to an Xilinx FPGA image file suitable for evaluation on our E7T development platform.

This tool chain is based heavily around Xilinx's free ISE WebPACK. See the ISE WebPACK page on the Xilinx website for more details and downloads.

(See our downloads page for details of building a Xilinx download cable)

Synthesis Tools

The synthesis tool converts the VHDL or Verilog code to a technology specific (Xilinx in our case) netlist (or netlists). This netlist is then passed to the Xilinx implementation tools in order to continue the process of translation to an FPGA image file. There are currently 4 options for synthesis tools that are seamlessly integrated into the Xilinx design flow, Xilinx's XST and three 3rd party synthesis tools.

Xilinx's XST

XST (Xilinx Synthesis Technology) is an FPGA synthesis tool from Xilinx (http://www.xilinx.com) that allows the synthesis of a VHDL or Verilog (but not a mixed-VHDL/Verilog) design to a Xilinx NGC netlist file. The really nice thing about XST is its price, is it free and part of the ISE WebPACK software suite.

3rd Party Synthesis Tools

There are currently three 3rd Party synthesis tools that integrate seamlessely with Xilinx's tool chain, namely:

• FPGA Express from Synopsys (http://www.synopsys.com/)
• LeonardoSpectrum from Mentor Graphics (http://www.mentor.com/synthesis/)
• Synplify from Synplicity (http://www.synplicity.com/)

Each tool has its own merits, but all will synthesize a VHDL, Verilog or mixed-VHDL/Verilog design to an EDIF netlist ready for the Xilinx implementation tools. All these synthesis tools can also synthesise designs for non-Xilinx FPGAs.

Xilinx Implementation Tools

The Implementation tools take the netlist generated by the chosen synthesis tool and perform the steps necessary to produce the FPGA programming file. All the tools required are included in the ISE WebPack software suite and are called automatically from the Xilinx project manager.

Translate

This is the first stage in the implementation process. The Translate stage takes the EDIF or NGC netlist (or netlists) from the synthesis stage, combines it with the constraints file and produces a single Xilinx NGD (Native Generic Database) file.

Map

The Map stage first performs a logical design rule check on the NGD file produced. by the translate process. Then the Map stage maps the logic in the NDG file to the components (logic cells, I/O cells and so on) available in the target FPGA. The output from this stage is a NCD (Native Circuit Description) file, this file represents the design implemented with the components available in the FPGA.

Place & Route

The Place & Route stage takes the NCD file from the Map stage and places the components in fixed positions in the FPGA. Then it routes the required connections between the placed components using the FPGA's routing channels. The output from this stage is another NCD file, but with all the placement and routing data included.

Generate Programming File

This stage takes the NCD file from the Place & Route stage and generates a file suitable for configuring the FPGA. For the E7T development platform, this file is a BIT (bitstream) file. This file may be used directly to configure the FPGA using a Xilinx programming cable, or optionally compressed using gzip and downloaded into the program FLASH on the Evaluator-7T board, where it will be used by RedBoot (the bootstrap firmware) to configure the FPGA.