ASIC & FPGA Cores

Sweeney Design is continually developing a range of reuasble IP cores. Our IP cores are designed to accelerate product development and reduce time-to-market. To this end each core is supplied with an eCos device driver, which is intended to allow the IP cores to be integrated into an embedded system using eCos with minimal effort. If eCos is not being used on the target system, the eCos drivers still serve as an excellent starting point for writing the drivers for your chosen embedded OS.

All our IP cores are available with flexible business models.

Each core is supplied with:

• Full VHDL source code or Netlist only
• Complete datasheet
• Industry standard PVCI processor interface
• Self-checking VHDL testbench
• eCos device driver

Also supplied in order to evaluate the core on our E7T Development System:

• Pre-built FPGA image (Xilinx .bit file) ready for download
• Pre-build eCos based demo application ready for download
• Complete sources for extra VHDL, including PVCI to KS32C50100 bridge
• Complete sources for demo application
• Constraints file for Xilinx tools (.ucf file)

See the HTML navigation file for the StdUart IP core (as found on the StdUart IP core CD) for an example of the deliverables.

For our usual licence terms, see our single project licence (PDF format).

Available Cores

Watchdog: Miprocessor Watchdog Timer

The Watchdog is a simple microprocessor watchdog timer.

Build-time options:

• Configurable read accesses - 1 or 2 cycle reads.
• Variable clock divider to allow a wide variety of clock frequencies to be supported.

Features:

• Programmable reset pulse width.
• Programmable reset timeout delay.
• Immediate system reset control.
• Keeps a count of watchdog resets.
• Core uses a single clock domain.
• Processor interface compliant with Industry standard Peripheral Virtual Component Interface (PVCI).

Watchdog IP Core Datasheet

Watchdog Evaluation Kit

The following downloads contain everything that is required to run and evaluate the Watchdog IP core on the E7T Development Platform. The kit consists of a device driver for eCos and pre-built FPGA image for the E7T-DBoard FPGA. See the device driver and FPGA image datasheets for further details.

StdUart: Standard Universal Asynchronous Receiver/Transmitter With FIFOs.

The StdUart is a UART IP core based on the industry standard 16550 UART.

Build-Time Options:

• Configurable transmit FIFO depth: 1 to 256 bytes (16 by default)
• Configurable receive FIFO depth: 1 to 256 bytes (16 by default)
• Configurable receive FIFO interrupt trigger levels.
• Configurable read accesses - 1 or 2 cycle reads.

Features:

• Compatible with all existing 16550 UART driver software.
• 16 byte (by default) transmit FIFO.
• 16 byte (by default) receive FIFO with error flags.
• Programmable baud rate generator.
• 5, 6, 7, or 8 bit character length.
• Even, odd, forced-1, forced-0, or no parity bit generation and checking.
• 1, 1.5, or 2 stop bit generation.
• Line break generation and detection.
• Polled and interrupt operation supported.
• Modem control signals nCTS, nRTS, nDSR, nDTR, nDCD, and nRI supported.
• Internal loop-back mode for self test.
• Core uses a single clock domain.
• Processor interface compliant with Industry standard Peripheral Virtual Component Interface (PVCI).

StdUart IP Core Datasheet

StdUart Evaluation Kit

The following downloads contain everything that is required to run and evaluate the StdUart IP core on the E7T Development Platform. The kit consists of a device driver for eCos and pre-built FPGA image for the E7T-DBoard FPGA. See the device driver and FPGA image datasheets for further details.